1. Field of the Invention
The present invention generally relates to the field of semiconductor devices, and more particularly to a lateral diffused metal-oxide-semiconductor (LDMOS) transistor.
2. Description of the Prior Art
Power semiconductor devices are currently being used in many applications. Such power devices include high-voltage integrated circuits which typically include one or more high-voltage transistors, often on the same chip as low-voltage circuitry. A commonly used high-voltage component for these circuits is the lateral double diffused MOS transistor (LDMOS). LDMOS structures used in high-voltage integrated circuits may generally be fabricated using some of the same techniques used to fabricate the low voltage circuitry or logic circuitry. In general, existing LDMOS structures are fabricated in a thick epitaxial layer of opposite conductivity type to the substrate.
High-power applications have called for the use of such lateral double diffused MOS transistors primarily because they possess lower "on" resistance, faster switching speed, and lower gate drive power dissipation than their bi-polar counterparts. These devices have heretofore also been strongly associated with bi-polar based process flows when integrated into a Bi-CMOS environment.
On the development of ultra-large-scale-integrated (ULSI), layout rule will shrink and the application of product is going to invent on multi-chip of integrated function. The prior LDMOS transistor is implemented by LOCOS process. Referring to FIG. 1, an N type well 112 and a P type well 110 with lighter concentration are formed in a P type substrate 100, and a field oxide (fox) region 120 is formed between gate 140 and source/drain 114A. However, this process could not meet the requirement of the layout rule for ULSI.